In digital data systems in general and in computer and telecommunications systems in particular, there is an ever-increasing drive for larger bandwidth and higher performance. These systems are comprised of discreet integrated circuit chips that are interconnected. Data moves through a chip and between chips in response to clock pulses, which, among other things, maintain synchronization of the data in parallel paths. At the extremely high data rates in today's systems, variations in the propagation of data over a bus along one path as compared to another path on the bus (i.e. skew) can exceed one clock cycle. U.S. Pat. No. 6,334,163, which is assigned to the assignee of this application and is incorporated herein by reference, discloses a so called Elastic Interface (EI) that can compensate for bus skew greater than one clock cycle without a performance penalty. However, packaging technology has not been able scale up to match the performance and bandwidth of the chip and interface technologies. In order to reduce the number I/O terminals on a chip and the number of conductive paths in a bus between chips, the prior art transfers data at a so called Double Data Rate (DDR), in which data is launched onto the bus at both the rising and falling edges of the clock. This allows the same amount of data to be transferred (i.e. bandwidth) with only half the number of bus conductors and half the number of chip I/O ports, as compared with a system where data is transferred only on a rising or a falling clock edge. Here it should be noted, that only half the data as compared to bus with twice the conductors is sent on each edge, referred to as the odd and the even half for convenience.
Often a double data rate bus is used between one chip and a next chip and another double data rate bus is used between that next chip and a still another chip. This so called daisy chain of chips with double data rate interfaces, typically includes a chip or chips with a local clock frequency that is the same as the double data rate synchronous interface clock frequency. In the prior art as illustrated in FIG. 1, the odd and even half of the data is aligned at the receiver to the on chip clock and then later driven across the next interface at the double data rate frequency. This alignment or serialization step requires that part of the data wait for all parts of the data to become available to the receiving chip, which increases the latency of the data. The prior art DDR synchronous interface adds an extra cycle receiver delay to align data before sending data out to a DDR data driver. On the DDR data driver side, another cycle extra delay is also needed if signal arrive at the driver later than the DDR driver launch setup time (data arrive later than the driver Master latch clock rising edge). In order to process DDR data with the synchronous clock on chip, DDR data stream is pipelined through two separate internal data paths. One data path is for the data corresponding to the half clock cycle when the DDR synchronous clock is high (known as the Even data), the other data path is for the data corresponding to the half clock cycle when the DDR synchronous clock is low (known as the Odd data). The shortcomings of the prior art are that the Even data are delayed a cycle to line up with the Odd data at the DDR receiver output port then pipelined to the chip internal logic. At the last stage of the data path pipeline, the Odd data are held an extra half cycle before launching off the chip.